One of the most popular techniques of isolating adjacent active devices in modern integrated circuits is referred to as shallow trench isolation (STI). Such isolation techniques generally etch shallow trenches in the silicon substrate, fill the etched trenches with a dielectric material and then planarize the structure back to the silicon surface in the areas outside the trench. Active devices can then be built in the spaces or islands between the isolation regions.
FIGS. 1A-1D are simplified cross-sectional views of a partially completed integrated circuit illustrating a common STI formation process formed on a silicon substrate 10. Referring to FIG. 1A, a typical shallow trench isolation structure is created by first forming a thin pad oxide layer 12 over the surface of substrate 10 and then forming a silicon nitride layer 14 over pad oxide layer 12. The nitride layer acts as a hard mask during subsequent photolithography processes and the pad oxide layer provides adhesion of the nitride to the silicon substrate and protects the substrate when the nitride layer is removed near the end of the STI formation process.
Next, as shown in FIG. 1B, a series of etch steps are performed using standard photolithography techniques to pattern the nitride and oxide layers and form trenches 20 in silicon substrate 10. The photoresist (not shown) is then removed and a trench lining layer 16, such as an in situ steam generation (ISSG) oxide or other thermal oxide layer or a silicon nitride layer, is usually formed.
Referring to FIG. 1C, trenches 20 are then filled with an insulating material, such as gapfill silicon oxide layer 22, using a deposition process that has good gapfill properties. One or more additional steps including chemical mechanical polishing (CMP) are then used to remove nitride layer 14 and pad oxide layer 12 and level the gapfill oxide 22 to the top of the trench (surface 24) as shown in FIG. 1D. The remaining insulating oxide in the trenches provides electrical isolation between active devices formed on neighboring islands of silicon.
Most integrated circuits include some regions that are isolated by relatively narrow trenches, e.g., in the active areas 26 shown in FIGS. 1B-1D, along with some regions that are isolated by much wider trenches, e.g., in open areas 28, that may be an order of magnitude or more wider than trenches in the active areas. Additionally, the narrow-width trenches used in many integrated circuits have very high aspect ratios making the filling of trenches 20 one of the most challenging gapfill applications in the formation of the integrated circuit. The presence of both high-aspect-ratio, narrow-width trenches and relatively wide trenches in different parts of the silicon substrate make the filling of the trenches even more challenging.
A variety of different gapfill techniques have been developed to address such situations. Despite the many successes achieved in this area, semiconductor manufacturers are continuously researching alternative techniques to fill such gaps as well as improved techniques to fill the even more aggressive aspect ratio gaps that will likely be required in future processes.